A. Field of the Invention
The present invention relates to a semiconductor device and semiconductor device manufacturing method.
B. Description of the Related Art
To date, insulated gate bipolar transistors (IGBTs) have been in the public domain as power semiconductor devices used in industrial machines and automobiles, domestic electrical appliances, and the like. Among power semiconductor devices, IGBTs in particular have good gate control, and can achieve low on-state voltage owing to a conductivity modulation effect. Also, two kinds of structure are widely known as MOS gate (an insulated gate formed of metal-oxide-semiconductor) structures of a power semiconductor device, those being a planar gate structure wherein a MOS gate is provided in plate form on a semiconductor substrate, and a trench gate structure wherein a MOS gate is embedded inside a trench formed in a semiconductor substrate.
The trench gate structure can be provided with a finer cell structure than the planar gate structure. Also, the trench gate structure does not have a JFET region (a portion wherein current concentrates in a region sandwiched by neighboring p-type base regions) peculiar to the planar gate structure. Therefore, the on-state voltage can be reduced further in the trench gate structure than in the planar gate structure. Also, when the IGBT is in an on-state, the larger part of a drop in on-state voltage, which causes conduction loss, is a voltage drop in a drift layer. Therefore, increasing a so-called injection enhancement (IE) effect, wherein carriers (electrons and holes) are confined as far as possible to the drift layer, also leads to low on-state voltage.
As a front surface structure having the IE effect, for example, there is a structure (hereafter referred to as a first existing structure) wherein a plurality of trenches are disposed at a short pitch in a stripe form planar layout, and an n+-type emitter region and p++-type contact region are repeatedly alternately disposed at constant intervals in a region of a p−-type base region sandwiched by neighboring trenches (hereafter referred to as a mesa portion) in a first direction in which the trenches extend in stripe form. By adopting the first existing structure, the mesa portion can be miniaturized (the width (distance between trenches) of the mesa portion in a second direction perpendicular to the first direction reduced) in a state wherein the area occupied by the n+-type emitter region in the mesa portion is maintained, and the IE effect can thus be increased while maintaining on-state voltage Von.
Also, a structure (hereafter referred to as a second existing structure) wherein the p++-type contact region is disposed in a linear planar layout extending in the first direction in a central portion of the mesa portion, and the n+-type emitter region is disposed between the p++-type contact region and a trench, is such that a threshold voltage Vth rises due to encroachment of the p++-type contact region into a channel portion, because of which there is a limit to miniaturization of the mesa portion. Encroachment of the p++-type contact region into the channel portion means that the p++-type contact region is diffused into a portion of the p−-type base region sandwiched by the n+-type emitter region and an n−-type drift layer (a portion of the p−-type base region in the vicinity of a side wall of a trench in which the channel (n-type inversion layer) is formed). By adopting the first existing structure, miniaturization of the mesa portion is possible, while restricting a rise in the threshold voltage Vth, even when encroachment of the p++-type contact region into the channel portion occurs.
Next, a description will be given of an existing surface structure having the IE effect, with the first existing structure as an example. FIG. 17 is a plan view showing the planar layout of a trench gate structure of an existing semiconductor device. FIG. 18 is a sectional view showing the sectional structure along a section line AA-AA′ of FIG. 17. FIG. 19 is a sectional view showing the sectional structure along a section line BB-BB′ of FIG. 17. FIG. 20 is a sectional view showing the sectional structure along a section line CC-CC′ of FIG. 17. The section line AA-AA′ passes through a trench 103 and a p++-type contact region 107. The section line BB-BB′ passes through the trench 103 and an n+-type emitter region 106. The section line CC-CC′ passes through the n+-type emitter region 106 and p++-type contact region 107. A gate dielectric, interlayer dielectric, source electrode, and passivation film are omitted from FIG. 17.
As shown in FIGS. 17 to 20, a plurality of trenches 103 are provided penetrating a p−-type base region 102 to reach an n−-type drift layer 101. The plurality of trenches 103 are disposed in a stripe form planar layout. A gate electrode 105 is embedded across a gate dielectric 104 inside the trench 103. The n+-type emitter region 106 and p++-type contact region 107 are repeatedly alternately disposed at constant intervals in a mesa portion sandwiched between neighboring trenches 103, in a first direction in which the trenches 103 extend in stripe form. The n+-type emitter region 106 and p++-type contact region 107 are both of a width such as to reach the side wall of the trench 103 on either side in a second direction perpendicular to the first direction.
Next, a description will be given of an existing semiconductor device manufacturing method, with a case of forming the first existing structure as an example. FIGS. 21 to 23 are sectional views showing a state partway through manufacture of the existing semiconductor device. FIGS. 21 to 23 show sectional structures partway through manufacture along the section line CC-CC′ of FIG. 17. Firstly, as shown in FIG. 21, the p−-type base region 102, a trench, a gate dielectric, and a gate electrode are formed in the front surface side of a semiconductor substrate that forms the n−-type drift layer 101. Next, a resist mask (not shown) in which are opened portions corresponding to formation regions of the n+-type emitter region 106 is formed on the substrate front surface. Next, an ion implantation of an n-type impurity is carried out with the resist mask as a mask, thereby selectively forming the n+-type emitter region 106 at constant intervals in the first direction in a mesa portion sandwiched between neighboring trenches.
Next, as shown in FIG. 22, a resist mask 111 in which are opened portions corresponding to formation regions of the p++-type contact region 107 is formed on the substrate front surface. Intervals W101 on the mask between n+-type emitter regions 106 and p++-type contact regions 107 neighboring in the first direction are created at predetermined intervals. Next, an ion implantation 112 of a p-type impurity is carried out with the resist mask 111 as a mask. The dotted line in the vicinity of the surface of the p−-type base region 102 in FIG. 22 indicates the p-type impurity implanted by the ion implantation 112. The p++-type contact region 107 is formed by the ion implantation 112 between n+-type emitter regions 106 neighboring in the first direction, distanced from the n+-type emitter regions 106. Next, after the resist mask 111 is removed, the trench gate IGBT is completed by a thermal processing (thermal diffusion process) step for causing the impurity to diffuse, steps of forming the remaining portions that configure the element structure, and the like, being carried out.
Also, a structure wherein an emitter layer is provided in stripe form in a direction perpendicular to an effective gate trench region connected to a gate electrode and a dummy trench region separated from the gate electrode has been proposed as another surface structure having the IE effect (for example, refer to JP-A-2009-026797). JP-A-2009-026797 is such that, by optimizing trench pitch and emitter region width, the resistance of a reverse bias safe operating area (RBSOA) is secured, and variation of the saturation current is restricted.
Also, the following structure has been proposed as another surface structure having the IE effect. An n-type emitter region and p-type contact region with high impurity concentrations are alternately formed in contact with a trench side surface in the trench longitudinal direction (channel width direction) in the surface of a p-type base region. The p-type contact region has a pattern such that the p-type contact region is not in contact with an edge portion of the n-type emitter region in contact with the trench in a place where a channel is formed (for example, refer to JP-A-11-345969 (Paragraphs 0069 and 0177, FIG. 31)).
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.